HEY1011 HALF BRIDGE DRIVER SWITCH EVALUATION BOARD

Applicable to : HEY1011

                HD-000288-UG-A

HEY-HBDS-G-12D1-C USERS GUIDE

HEY1011 HALF BRIDGE BIPOLAR DRIVER SWITCH BOARD  

Description

The Heyday Integrated Circuits Half Bridge Driver-Switch HEY-HBDS-G-12D1-C is a demonstration board containing two HEY1011-L12C GaN FET drivers and two GaN FETs configured in a half bridge configuration.

The datasheet for the HEY1011-L12C in this board can be found here.

Figure 1: HEY-HBDS-G-12D1-C Evaluation Board

The HEY-HBDS-G-12D1-C can be used to perform double pulse tests, or to interface the half bridge to an existing LC power section, both as shown below.

The isolated HEY1011-L12C driver does not require secondary side power or bootstrap components.  Gate drive power is supplied to secondary side from the primary side supply voltage V_DRV.  The amplitude of the gate drive can be varied by varying V_DRV between 7 V and 15 V.

Contents

Description        1

Quick Start Guide        4

Gate pull up and pull down resistors        4

Enable and start sequence        5

Measurement points        6

Bipolar Gate Drive        6

Propagation Delay        7

Double Pulse Test        8

Double Pulse Test Results        9

DPT Result 100V – 15A        9

DPT Result 400V – 62A        10

HEY-HBDS-G-12D1-C SCHEMATIC        11

HEY-HBDS-G-12D1-C PCB Layout        12

HEY-HBDS-G-12D1-C Bill of materials        13

Disclaimer        14

Quick Start Guide

Figure 2:HEY-HBDS-G-12D1-C Quick Start

1. Apply V_DRV = 12V
2. Link pins EN_PU and EN (if not using external Enable control)
3. Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs.
4. Convenient test points a located on the test board as shown above.  A suitable differential oscilloscope should be used to monitor the high side gate signal from V_GH to V_SW.

Gate pull up and pull down resistors

The HEY1011-L12C gate driver has independent output pins for the gate pull up and gate pull down allowing control of the turn-on and turn-off rise and fall times.

The default values for these resistors are:

• OUTPU:        R1 and R5 = 10 Ohms
• OUTPD:        R3 and R7 = 1 Ohm

These values can be modified to suit your own application.

Enable and start sequence

The HEY1011-L12C has an open drain enable pin (EN) to facilitate a system level wired-AND start up.

When the enable pin is externally pulled low this forces the driver into a low power mode. The driver output is pulled low in this mode. In the event of an internal fault condition, such as UVLO, this pin is actively pulled low internally by the driver. During normal operation, the pin is released by the driver, and must be pulled high with an external pull-high resistor. This functionality can be used by the PWM controller as an indication that it can start sending IN pulses to the driver. It is typically wired AND with the controller enable pin as shown in Figure 3Error! Reference source not found. below.

The HEY-HBDS-G-12D1-C EVM board provides direct access to the EN pin on connector CONN1.  Internally the board contains a 100k pull up resistor connected from VDRV to the EN_PU pin on connector CONN1 – see schematic in Figure 12. If external control of the enable function is not required, pins EN and EN_PU must be linked together on CONN1 to make use of the internal 100k pull up resistor to enable the driver.  If the EN pin is left floating, the drivers will not respond to INL or INH input signals.

Figure 3:HEY1011-L12C Wired-AND enable

The start up sequence of the HEY1011-L12C is shown in Figure 4 below.  Time T_START is defined as the time after which V_DRV reaches the UVLO rising level to the HEY1011-L12C releasing the EN internal pull down.

IMPORTANT the IN signal must not be applied before the EN pin has been released.

Figure 4: HEY1011-L12C Start up sequence.

Measurement points

The HEY-HBDS-G-12D1-C EVM contains convenient test points for monitoring the high and low side gate drives as well as the switch node as shown in Figure 5 below.

When measuring V_{GS_H} use a differential probe with suitable ratings for the applied bus voltage.  The HEY-HBDS-G-12D1-C EVM uses a bipolar gate drive arrangement as shown in Figure 6 below.  When measuring V_GS, both gate drives are measured relative to the source of their associated GaN FET.  Therefore, the off-state voltage will be negative.

It is important to use a low inductance scope probe ground lead as shown to avoid pickup of spurious switching noise.

Bipolar Gate Drive

Due to the high rate of change of voltages and currents in power switching circuits, unwanted inductor currents and capacitor voltage drops can be created.

One such example is the false turn on of a FET due to a dv/dt event.  In a half bridge circuit, after the low side FET has been turned off and a suitable dead-time elapsed, the high side FET is turned on.  This produces a rapidly changing switch node voltage at the drain of the low side FET.  This voltage will produce a capacitor current:

flowing in the gate-drain capacitance, C_GD, and driver output.  It will cause the voltage on the gate of the low side FET to rise.  If this voltage spike peaks beyond the threshold voltage V_TH, the FET will conduct.  Considering that the high side FET is also conducting, this can result in a potentially destructive shoot-through event.

The HEY-HBDS-G-12D1-C EVM uses a bipolar gate drive arrangement which is useful to mitigate against the effects of gate-drain capacitor currents. The secondary supply voltage V_SEC is a function of the primary supply voltage V_DRV.  The zener diode, CR1, will regulate the positive turn on voltage of the GaN FET.  During the turn-off of period, the gate voltage will be negative with a value of:

V_{GS_OFF} = V_SEC – V_ZENER.  V_SEC is typically 9 V.

 This negative V_{GS_OFF} voltage allows more margin before the threshold voltage can be reached.

Figure 6: Bi-polar gate drive schematic

Propagation Delay

• V_DRV = 12V
• Input = 100kHz
• R_PU = 10R, R_PD = 1R
• Power train un-loaded.  That is, VHV+ = 0V.

Figure 7: Typical Driver output at 100kHz

Double Pulse Test

The double pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner.

For a low side switch the setup is as shown below:

Figure 8: Double Pulse Test

The low side switch is driven with two pulses as shown below.  The high side switch can be held off or driven with the inverse of the low side gate switch (with adequate dead time).

Figure 9: Double Pulse Test Waveforms

An inductor is placed in parallel with the high side switch.  The goal of this inductor is to establish the test level current in the low side switch at the end of the first on pulse (1).  The magnitude of the test level current at the end of period 1 is given by:

During period 2, the inductor current will naturally decay.  The duration of period 2 should not be too long that inductor current deviates significantly from the desired test level.

During period 3, the inductor current will again rise.  Period 3 should not be so long that the inductor current rises to an excessive level.

The falling edge of pulse 1 is used to examine the hard turn off characteristics of the switch.  The rising edge of pulse 3 is used to examine the hard turn on characteristics of the switch.  By only applying these two pulses, the switches are only on for a very short time and should not overheat.

Double Pulse Test Results

DPT Result 100V – 15A

Figure 10: DPT 100V – 15A

DPT Result 400V – 62A

Figure 11: DPT 400V – 62A

HEY-HBDS-G-12D1-C SCHEMATIC

Figure 12: HEY-HBDS-G-12D1-C Schematic

HEY-HBDS-G-12D1-C PCB Layout

Figure 13: HEY-HBDS-G-12D1-C Silkscreen and component placement

Figure 14: HEY-HBDS-G-12D1-C Top Side Copper (L) and Layer 2 Copper (R)

Figure 15: HEY-HBDS-G-12D1-C Layer 3 Copper(L) and Bottom Side Copper (R)

HEY-HBDS-G-12D1-C Bill of materials

Table 1:  Bill of materials:

Disclaimer

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 Users Guide:HEY1011 HALF BRIDGE DRIVER SWITCH EVALUATION BOARD        - All information subject to change -  of

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