HBDS-G-12K1-A - Half Bridge Bipolar Driver-Switch Board

HEY-HBDS-G-12K1-A USERS'GUIDE

HEY1011 HALF BRIDGE BIPOLAR DRIVER SWITCH BOARD

Content

Description - Quick Start Guide - Default Settings - Gate pull up and pull down resistors - 3V3 LDO For Logic Circuits - HEY1011-L12 Under Voltage Lockout - Input PWM Circuit - Enable and start sequence - Measurement points - Bipolar Gate drive - Propagation delay - Double Pulse Test - Double pulse test results - Schematic - PCB Layout - Bill of materials - Ordering Information - Disclaimer

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Description

The Heyday Integrated Circuits Half Bridge Driver-Switch HEY-HBDS-G-12D1-D is a demonstration board containing two HEY1011-L12 GaN FET drivers and two GaN FETs configured in a half bridge configuration.

The datasheet for the HEY1011-L12 used in this board can be found here.

Fig1- HEY-HBDS-G-12K1-A Evaluation Board

Figure 1: HEY-HBDS-G-12K1-A Evaluation Board

The HEY-HBDS-G-12D1-D can be used to perform double pulse tests, or to interface the half bridge to an existing LC power section, both as shown below.

The isolated HEY1011-L12 driver does not require secondary side power or bootstrap components. Gate drive power is supplied to secondary side from the primary side supply voltage V_DRV. The amplitude of the gate drive can be varied by varying V_DRV between 7 V and 13.2 V.

hazard

DANGER

DO NOT TOUCH THE BOARD WHEN IT IS ENERGIZED AND ALLOW ALL COMPONENTS TO DISCHARGE COMPLETELY PRIOR HANDLING THE BOARD.

HIGH VOLTAGE CAN BE EXPOSED ON THE BOARD WHEN IT IS CONNECTED TO POWER SOURCE. EVEN BRIEF CONTACT DURING OPERATION MAY RESULT IN SEVERE INJURY OR DEATH.

Please ensure that appropriate safety procedures are followed. This evaluation kit is designed for engineering evaluation in a controlled lab environment and should be handled by qualified personnel ONLY. Never leave the board operating unattended.

WARNING

Some components can be hot during and after operation. There is NO built-in electrical or thermal protection on this evaluation kit. The operating voltage, current, and component temperature should be monitored closely during operation to prevent device damage.

CAUTION

This product contains parts that are susceptible to damage by electrostatic discharge (ESD). Always follow ESD prevention procedures when handling the product.

Input PWM Circuit

The HEY-HBDS-G-12K1-A EVM contains an on-board circuit to generate a deadtime between the high side and low side gate drive signals from a single external signal generator.

This option is selected by setting the connector CONN8 jumpers to HS_INT and LS_INT. The deadtime between the high side and low side can be adjusted with the variable resistors R16 and R17 and the minimum deadtime is set with resistors R18 and R19.

Alternatively, the input PWM signals can be supplied externally direct from two signal generator channels and the internal deadtime circuit is bypassed by selecting HS_EXT and LS_EXT on connector CONN8.

Figure 5: Input signal deadtime circuit

Enable and start sequence

The HEY1011-L12 has an open drain enable pin (EN) to facilitate a system level wired-AND start up.

When the enable pin is externally pulled low this forces the driver into a low power mode. The driver output is pulled low in this mode. In the event of an internal fault condition, such as UVLO, this pin is actively pulled low internally by the driver. During normal operation, the pin is released by the driver, and must be pulled up with an external pull-up resistor. This functionality can be used by the PWM controller as an indication that it can start sending IN pulses to the driver. It is typically wired AND with the controller enable pin as shown in Figure 7 below.

The HEY-HBDS-G-12K1-A EVM board provides direct access to the EN pin on connector CONN1.

The EVM also contains, on connector CONN 5, options for pulling the EN pin to VDRV, an internal 3.3 V or an external EN_PU supply rail on CONN1. The EN_PU option can be used to use an external DC source or external system voltage, to pull up the EN pin.

The fourth option on connector CONN5 ties EN to GND and disables both drivers

Figure 6: Enable pull up options

Internally the board contains a 10k pull up resistor connected to the EN pin. If the EN pin is left floating, the drivers will not respond to INL or INH input signals.

Figure 7: HEY1011-L12 Wired-AND enable

The start up sequence of the HEY1011-L12 is shown in Figure 8 below. Time T_START is defined as the time after which V_DRV reaches the UVLO rising level to the HEY1011-L12 releasing the EN internal pull down.

IMPORTANT the IN signal must not be applied before the EN pin has been released.

Figure 8: HEY1011-L12 Start up sequence.

Typical Enable/Disable

When disabling the HEY1011, the output gate drive is terminated synchronous to the EN signal falling edge as shown in Figure 9 (left) below.

When the driver is enabled, the output gate is synchronous to the first rising edge of the IN signal that occurs after the secondary VSEC UVLO level is reached as shown in Figure 9 (right) below.

fig9a

fig9b

CH1 (Red): Enable
CH2 (Grn): Low side switch V_GS
CH3 (Blk): PWM Input

Disable

Enable

Figure 9: Typical Driver disable and enable

Measurement points

The HEY-HBDS-G-12K1-A EVM contains convenient test points for monitoring the high and low side gate drives as well as the switch node as shown in Figure 10 below.

When measuring V_{GS_H} use a differential probe with suitable ratings for the applied bus voltage. The HEY-HBDS-G-12K1-A EVM uses a bipolar gate drive arrangement as shown in Bipolar Gate Drive below. When measuring V_GS, both gate drives are measured relative to the source of their associated GaN FET. Therefore, the off-state voltage will be negative. See section Bipolar Gate Drive for further details.

It is important to use a low inductance scope probe ground lead as shown to avoid pickup of spurious switching noise.

Figure 10: Measurement points

CAUTION:
Many of the test signals have different reference voltages. It is important that these are not short circuited through the oscilloscope ground leads or external test equipment

Bipolar Gate Drive

Due to the high rate of change of voltages and currents in power switching circuits, unwanted inductor currents and capacitor voltage drops can be created.

One such example is the false turn on of a FET due to a dv/dt event. In a half bridge circuit, after the low side FET has been turned off and a suitable dead-time elapsed, the high side FET is turned on. This produces a rapidly changing switch node voltage at the drain of the low side FET. This voltage will produce a capacitor current:

flowing in the gate-drain capacitance, C_GD, and driver output. It will cause the voltage on the gate of the low side FET to rise. If this voltage spike peaks beyond the threshold voltage V_TH,the FET will conduct. Considering that the high side FET is also conducting, this can result in a potentially destructive shoot-through event.

The HEY-HBDS-G-12K1-A EVM uses a bipolar gate drive arrangement which is useful to mitigate against the effects of gate-drain capacitor currents. The secondary supply voltage V_SEC is a function of the primary supply voltage V_DRV. The zener diode, CR1, will regulate the positive turn on voltage of the GaN FET. During the turn-off of period, the gate voltage will be negative with a value of:

V_{GS_OFF} = V_SEC – V_ZENER. V_SECis typically 8 V when V_DRV = 12 V and C_LOAD = 1 nF.

This negative V_{GS_OFF} voltage allows more margin before the threshold voltage can be reached.

Figure 11: Bi-polar gate drive schematic

Double Pulse Test

The double pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner.

For a low side switch the set up is as shown below:

Figure 13: Double Pulse Test

The low side switch is driven with two pulses as shown below. The high side switch can be held off or driven with the inverse of the low side gate switch (with adequate dead time).

Figure 14: Double Pulse Test Waveforms

An inductor is placed in parallel with the high side switch. The goal of this inductor is to establish the test level current in the low side switch at the end of the first on pulse (1). The magnitude of the test level current at the end of period 1 is given by:

During period 2, the inductor current will naturally decay. The duration of period 2 should not be too long that inductor current deviates significantly from the desired test level.

During period 3, the inductor current will again rise. Period 3 should not be so long that the inductor current rises to an excessive level.

The falling edge of pulse 1 is used to examine the hard turn off characteristics of the switch. The rising edge of pulse 3 is used to examine the hard turn on characteristics of the switch. By only applying these two pulses, the switches are only on for a very short time and should not overheat.

Double Pulse Test Results

COMPONENTS
Drivers:	Heyday HEY1011-L12
Inductor:	100uH Air Core
R_PU:	10Ω
R_PD:	1Ω