AHV85000 + AHV85040

GaN FET Isolated Gate Driver Chipset with Power-Thru Integrated Isolated Bias Supply

FEATURES AND BENEFITS

• Chipset transmits both PWM signal & bias power through a single external isolation transformer
• 50 ns propagation delay (with recommended transformers)
• Separate drive output pins: pull-up (2.8 Ω) and pull-down (1.0 Ω)
• Supply voltage 7 V < VDRV < 13.2 V
• Undervoltage lockout on primary VDRV and secondary VSEC
• Enable pin with fast response
• Continuous ON capability—no need to recycle IN or recharge bootstrap capacitor
• CMTI > 100 V/ns dv/dt immunity (with recommended transformers)
• Creepage distance > 4 or 8 mm (with recommended transformers)
• AC-DC and DC-DC converters: Totem-pole PFC, LLC half-/full-bridge, SR drive, multi-level converters, phase-shifted full-bridge, high-side cutoff switches
• Three-phase: Vienna rectifier, T-type inverter
• Industrial: transportation, robotics
• Grid Infrastructure: micro-inverters, solar

• No high-side bootstrap
• No external secondary-side bias supply

APPLICATIONS

PACKAGE

Not to scale

DFN10 3x3 mm EJ package

DESCRIPTION

The AHV85000 & AHV85040 is a cost-optimized isolated gate drive chipset for GaN FET devices. When combined with one of the recommended external transformers, it provides a self-powered isolated gate drive solution, ideal for GaN FETs in multiple applications and topologies. A selection of recommended third-party transformers is available, each optimized for different drive voltage and gate charge characteristics, including E-mode GaN (6-V drive) and Cascode-GaN (12-V drive).

The chipset transmits both PWM signal and gate bias power through the external transformer, eliminating the need for any external gate drive auxiliary bias supply or high-side bootstrap. This greatly simplifies the system design and reduces EMI through reduced total common-mode (CM) capacitance. It also allows the driving of a floating switch in any location in a switching power topology.

The chipset enables fast propagation delay and high peak current source/sink capability to efficiently drive GaN FETs in high-frequency designs. High CMTI combined with isolated outputs for both bias power and drive make it ideal in applications requiring isolation, level-shifting, or ground separation for noise immunity.

The chipset is available in a pair of 3x3 mm DFN10 surface-mount packages. Several protection features are integrated, including undervoltage lockout on primary and secondary bias rails, internal pull-down on IN pin and OUTPD pin, and a fast-response enable input/fault-output pin.

TYPICAL APPLICATION

Figure 1: Typical AHV85000/040 chipset half-bridge — eliminates high-side bootstrap.

AHV85000/040-DS        Advance Information Datasheet • Subject to Change Without Notice        October 20, 2022

ABSOLUTE MAXIMUM RATINGS (AHV85000, AHV85040)^[1]

[1] Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

[1] Additional thermal information available on the Allegro website.

RECOMMENDED OPERATING CONDITIONS: Valid at –40°C < TJ < 125°C, 10.5 V < VDRV < 13.2 V, CSEC = 22 nF, COUT = 1 nF,

unless otherwise stated

MSL RATING

Per JEDEC J-STD-033C, the AHV85110 devices are rated MSL3. This MSL3 rating means that once the sealed production packaging is opened, the devices must be reflowed within a “floor-life” of 168 hours (1 week) if they are stored in under standard ambient conditions (30°C and 60% relative humidity (RH)).

The peak reflow temperature should not exceed the maximum specified in MSL Rating table.

If the devices are exposed to the standard ambient for more than 168 hours, they must be baked before reflow to remove any excess moisture in the package and prevent damage during reflow soldering. The required bake times and temperatures are detailed in IPC/JEDEC standard J-STD-033C. If the devices are exposed to higher temperature and/or RH compared to the standard ambient of 30°C/60% RH, the floor-life will be shortened due to the increased rate of moisture absorption. If the actual ambient conditions exceed the standard ambient, it is recommended that parts should always be baked per IEC/JEDEC J-STD-033C before reflow as a precaution to avoid potential device damage during reflow soldering.

FUNCTIONAL BLOCK DIAGRAM

Figure 2: AHV85000 & AHV85040 Block Diagrams

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Package EE Pinout

Terminal List Table

TYPICAL APPLICATIONS

Figure 3: Half-bridge with AHV85000 + AHV85040 chipset as high and low side drivers

ELECTRICAL CHARACTERISTICS: Valid at –40°C < TJ < 125°C, 7.0 V < VDRV < 13.2 V, CSEC = 22 nF, COUT = 1 nF,

unless otherwise stated

[1] Not tested in production; guaranteed by design and bench characterization.

[2] When VDRV is below the UVLO threshold, the driver output is actively held low.

SWITCHING CHARACTERISTICS: Valid at –40°C < TJ < 125°C, 7.0 V < VDRV < 13.2 V, CSEC = 22 nF, COUT = 1 nF,

unless otherwise stated

VSEC PIN CAPACITOR

[1] Smaller CSEC values than the recommended typical value can give higher voltage ripple on C_SEC. Recommended C_SEC value is 10-20 times larger than the effective load capacitance C_OUT

[2] Larger CSEC values will mean longer startup times.

FUNCTIONAL DESCRIPTION

 The AHV85000/AHV85040 is a is a self-powered isolated gate driver chipset leveraging Allegro’s patented Power-Thru technology. The technology  allows the transfer of both PWM signal and gate power across a single transformer-based isolation barrier. This eliminates the need to provide an isolated bias supply to power the isolated side of the driver, greatly simplifying the system design. Only an external decoupling capacitor is required on the isolated side. The chipset has been optimized for driving the gate of typical Schottky-gate Enhancement-mode (E-mode) GaN FETs, such as those available from GaN Systems, Innoscience, ST, Nexperia, GaN Power International, Taiwan Semiconductor, Rohm and others. In addition, some Transphorm cascode-GaN devices can also be driven, where low-voltage logic-level MOS devices are used inside the cascode. An online FET selection tool can be downloaded from the Allegro website to assist system designers, to check compatibility of various FET devices with the driver. The maximum drive capability is 30 nC at 6 V VGS. The isolated VSEC bias rail on the secondary is derived open-loop from the primary 12 V supply VDRV. The VSEC rail level regulates quite well versus PWM switching frequency FSW at the IN pin, for a given fixed VDRV level, and for a fixed load COUT at the OUTx drive pins (the load presented by the gate of the GaN FET being driven). This is because the charge delivered per PWM cycle naturally increases in tandem with the charge consumed by the FET gate, so there is a good charge balance across a wide frequency range. However, the VSEC rail does vary with effective loading of the gate of FET being driven; as VSEC level falls, more charge is available to be delivered to the secondary side, while the charge consumed by the FET gate decreases with falling VSEC level. Therefore, the VSEC rail will droop as far as needed until the charge delivered matches the charge consumed. For this reason, it’s also very important to minimize the amount of charge diverted into any external loads. For example, a very low bias power external circuit can be powered using VSEC, but the consumption should be minimal, to minimize the charge diverted away from the gate of FET. Similarly, if a gate-source pull-down resistor is desired on the load FET (to prevent false turn-on in the case of a manufacturing fault, such as an open-circuit gate turnon resistor), the resistor value should be as large as possible. The recommended value is 100 kΩ, to minimize DC loading on VSEC. Since DC load current converts to equivalent charge as Q = I × t, DC loading effects will become significantly more pronounced at lower PWM frequency, as the time duration t gets longer. Since there is just a single magnetic isolation barrier to transfer both PWM signal and gate power, this also greatly reduces the total parasitic capacitance between the primary-side and isolatedside, to typically < 1 pF total for both signal and power channels. This is much less than the typical total parasitic capacitance value for a solution using a conventional isolated gate driver with a separate isolated DC-DC bias supply, where the capacitance contribution from the DC-DC isolation transformer could be as high as 10 pF or more. This reduction in isolation capacitance greatly reduces the level of noise injected back into the low-voltage control circuit by the high-voltage and high dv/dt switching nodes in the power stage half-bridge legs, reduces system level Common-Mode (CM) EMI, and saves on power loss that occurs through repetitive charging and discharging of this parasitic capacitance between the high bus voltage level and ground.

APPLICATIONS INFORMATION

External Transformer Details

The AHV85000 and AHV85040 chipset form the primary-side transmitter (TX) and secondary-side receiver (RX) for an isolated GaN FET gate-driver. The chipset relies on an external transformer, connected between the TX and RX ICs, to achieve the isolated transmission of both PWM signal and gate bias power to the secondary side. The required transformer consists of a simple 2-winding, 4-pin structure – a primary-referenced TX winding and a secondary-referenced RX winding.

A selection of recommended transformers is listed below, along with the manufacturer and the orderable part number. Each transformer has been designed and optimized to work with the AHV85000/AHV85040 chipset interchangeably. The desired transformer can be selected to suit system design requirements, e.g. depending on the required system creepage distance, isolation rating, and the target GaN FET drive voltage and gate charge.

Table of recommended transformers

Expert designers can choose to use a custom transformer design of their own. The table below lists the acceptable ranges of the key transformer parameters that must be adhered to, to ensure compatibility with the AHV85000/AHV85040 chipset.

Table of required transformer parameters

Bidirectional Enable/Disable EN Pin

EN is a bidirectional open-drain pin which requires an external resistor pull-up to the VDRV pin or a suitable logic supply > 3.3 V. The EN pin allows for management of startup and fault conditions between the PWM controller and multiple drivers, through use of a shared enable EN line. Either the PWM controller or the driver can pull the EN pin low via the EN bus, as shown in Figure 8. When the EN pin is pulled low (either externally or internally), this forces the driver into a mode where the IN pin signal is ignored, and the OUT pins are disabled and actively pulled low. When the EN pin goes high, normal driver operation is enabled.

In the event of an internal driver fault condition, such as UVLO or normal startup delay, the EN pin is actively pulled low internally by the driver. This driver pull-down can be detected by the PWM controller and used as a flag for an external fault, or to flag that the driver is ready, and PWM can commence.

Figure 8: Example ‘Wired-AND’ connection between driver and controller

The shared EN line is typically wired-AND with the controller EN pin, as shown in Figure 8. Multiple drivers can be connected in parallel with the controller on the shared EN line, such that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe startup of the system.

Note that the EN pin has no internal pull-up or pull-down—the open-drain configuration relies on an external pull-up resistor for normal operation. Similarly, the EN pin must be actively pulled low externally to disable the driver. The EN pin should never

be left floating. If not used, the EN pin should be connected to VDRV through a pull-up resistor in a recommended range of 10 to 100 kΩ. The EN pin dv/dt when being pulled low or high should be at least 0.1 V/μs.

When the EN pin is pulled low, the driver output is disabled, and pulls down the OUTPD pin, regardless of the IN pin level (high or low). The driver goes to a low-power standby mode, and the isolated VSEC bias rail is allowed to discharge. The rate of decay of VSEC depends on the value of the CSEC capacitor.

When the EN pin is subsequently pulled high, the driver will re-enable, and the isolated VSEC bias rail will start to recharge.

Even if the IN pin is connected to a PWM signal, the OUT pins will not respond until the VSEC rail exceeds the secondary UVLO threshold. The rate of rise of VSEC depends on the PWM frequency at the IN pin. Worst-case slowest rise time is

when IN = 0, using the slowest internal energy-transfer mode. In this mode, the rise time will be approximately 80 μs for CSEC of 47 nF to charge from zero to the rising UVLO threshold.

Startup and Shutdown Procedures

Any PWM signal applied to IN must remain low until VDRV > UV threshold, to avoid parasitic charging of the VDRV rail

through the IN pin internal ESD structures. After VDRV exceeds the UV enable threshold, a startup time delay tSTART is required to charge VSEC and allow all internal circuits to initialize and stabilize. During tSTART, any IN signal inputs are ignored. EN internal pull-down will remain active during tSTART, and will disable (i.e., go open-drain) only when VDRV has reached its UVLO voltage level, all on-chip voltages are stabilized, and the internal tSTART timer has elapsed. Thus, the EN pin can be used via a shared EN line to flag when tSTART has elapsed, and the driver is ready to respond to PWM signals at the IN pin, as outlined above.

Figure 9: Startup relationship to be observed between VDRV, EN, and IN PWM signal.

Operating Frequency

The maximum allowable operating frequency of the AHV85000/AHV85040 chipset is dependent on the operating ambient air temperature, VDRV level, and the gate charge of the external GaNFET being driven at the OUTPU/OUTPD pins. The total power transferred from VDRV on the primary to the external GaNFET on the secondary increases with gate drive switching frequency and VDRV, hence the IC packages must dissipate more heat. The external transformer selection or custom design must be appropriate for the maximum required PWM frequency required in the system. Maximum allowable PWM frequency is 800 kHz, subject to sufficient heatsinking of the primary and secondary side ICs.

V_DRV and C_SEC Design Guidelines

The output gate drive amplitude is always less than VDRV. The OUTPU gate voltage level depends on factors such as VDRV level, CLOAD, and CSEC. Figure 11 shows the typical output gate drive amplitude as a function of VDRV and CLOAD, for an assumed value of CSEC as a multiple of CLOAD, for a 50% duty cycle PWM at the IN pin. This assumes a 1:1 transformer ratio setting, for the 6-V E-Mode type GaN applications.

Figure 11: Typical VGATE versus VDRV for four CLOAD capacitors;

Conditions: Np/Ns 1:1, fIN = 100 kHz, D = 50%, CSEC = 20×CLOAD

The recommended value for CSEC is approximately 10 to 20 times CLOAD (the equivalent gate capacitance), to give approximately 5% to 10% switching ripple on the VSEC rail. Other values can be used; however, lower values will result is higher ripple on VSEC. Larger CSEC will require a longer startup time. The maximum recommended value of CSEC = 100 nF should not be exceeded.

Bipolar Output Drive

Bipolar output drive is used to limit the positive gate drive amplitude (relevant for E-Mode type GaN), and also provides a negative off-state gate voltage which can be beneficial in protecting against false turn on due to parasitic circuits components. It can be added simply to the AHV85040 by including three extra small external components.

Figure 12: AHV85040 bipolar output drive implementation with external Zener

PACKAGE OUTLINE DRAWING

Figure 13: AHV85000 & AHV85040 EJ Package Outline and Recommended Footprint

Complete package information can be downloaded from Allegro Microsystems website: https://www.allegromicro.com/en/design-support/packaging

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