DESCRIPTION
The AHV85110 isolated gate driver is optimized for driving GaN FETs in multiple applications and topologies. An isolated output bias supply is integrated into the driver, eliminating the need for any external gate drive auxiliary bias supply or high-side bootstrap. This greatly simplifies the system design and reduces EMI through reduced total common-mode (CM) capacitance. It also allows the driving of a floating switch in any location in a switching power topology.
The driver has fast propagation delay and high peak source/sink capability to efficiently drive GaN FETs in high-frequency designs. High CMTI combined with isolated outputs for both bias power and drive make it ideal in applications requiring isolation, level-shifting, or ground separation for noise immunity.
The device is available in a compact low-profile surface-mount NH package. Several protection features are integrated, including undervoltage lockout on primary and secondary bias rails, internal pull-down on IN pin and OUTPD pin, fast response enable input, and OUT pulse synchronization with first IN rising edge after enable (avoids asynchronous runt pulses).
Figure 1: LGA: 10 x 7.66 x 2.53 mm 12-pin integrated prototype package
Typical application diagram
Figure 2: Typical HEY1011 Half-Bridge application - eliminates high-side booststrap
TYPICAL APPLICATIONS
Figure 3: Half-Bridge with HEY1011 as high and low side drivers
Figure 4: Totem pole PFC: HEY1011 (GaN version) and HEY2011 (MOS version) as high side and low side drivers
Figure 5: Centre switched Flyback – HEY1011 driving centre tapped switch (symmetrical bipolar voltage swings)
Figure 6: Secondary control to primary drive - Hey1011 single driver
Figure 7: Multi-Level Converter – stacked low voltage switches results in higher efficiency. HEY1011 makes this easy to drive.
APPLICATIONS INFORMATION
Bidirectional Enable/Disable
EN is a bidirectional open-drain pin which requires an external resistor pull-up to the VDRV pin. The EN pin allows for management of start-up and fault conditions between the PWM controller and multiple HEY1011 drivers, through use of a shared enable EN line. Either the PWM controller or the driver can pull the EN pin low via the EN bus, as shown in Figure 9. When the EN pin is pulled low (either externally or internally), this forces the driver into a mode where the IN pin signal is ignored, and the OUT pins are disabled and actively pulled low. When the EN pin goes high, normal driver operation is enabled.
In the event of an internal driver fault condition, such as UVLO or normal start-up delay, the EN pin is actively pulled low internally by the driver. This driver pull-down can be detected by the PWM controller and used as a flag for an external fault, or to flag that the driver is ready, and PWM can commence.
The shared EN line is typically wired-AND with the controller Enable pin, as shown in Figure 9. Multiple HEY1011 drivers can be connected in parallel with the controller on the shared EN line, such that which means that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe start-up of the system.
Figure 9: Example ‘Wired AND’ connection between driver and controller
The shared EN line is typically wired-AND with the controller Enable pin, as shown in Figure 9. Multiple HEY1011 drivers can be connected in parallel with the controller on the shared EN line, such that which means that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe start-up of the system.
Note that the EN pin has no internal pull-up or pull-down – the open-drain configuration relies on an external pull-up resistor for normal operation. Similarly, the EN pin must be actively pulled low externally to disable the driver. The EN pin should never be left floating. If not used, the EN pin should be connected to VDRV through a pull-up resistor in a recommended range of 10-100 kΩ. The EN pin dv/dt when being pulled low or high should be at least 0.1 V/μs.
When the EN pin is pulled low, the driver output is disabled, and pulls down the OUTPD pin, regardless of the IN pin level (high or low). The driver goes to a low-power standby mode, and the isolated VSEC bias rail is allowed to discharge. The rate of decay of VSEC depends on the value of the CSEC capacitor.
When the EN pin is subsequently pulled high, the driver will re-enable, and the isolated VSEC bias rail will start to recharge. Even if the IN pin is connected to a PWM signal, the OUT pins will not respond until the VSEC rail exceeds the secondary UVLO threshold. The rate of rise of VSEC depends on the PWM frequency at the IN pin. Worst case slowest rise time is when IN = 0, using the slowest internal energy-transfer mode. In this mode the rise time will be approximately 80 μs for CSEC of 47 nF to charge from zero to the rising UVLO threshold.
Start up procedure
Figure 10: HEY1011 Start-up relationship to be observed between VDRV, EN and IN PWM signal
Any PWM signal applied to IN must remain low until VDRV > UV threshold, to avoid parasitic charging of the VDRV rail through the IN pin internal ESD structures. After VDRV exceeds the UV enable threshold, a start-up time delay Tstart is required, to charge VSEC and allow all internal circuits to initialise and stabilise. During Tstart, any IN signal inputs are ignored. EN internal pull-down will remain active during Tstart, and will disable (i.e. go open-drain) only when VDRV has reached its UVLO voltage level, all on-chip voltages are stabilised and the internal Tstart timer has elapsed. This the EN pin can be used via a shared EN line to flag when Tstart has elapsed, and the driver is ready to respond to PWM signals at the IN pin, as outlined above.
Operating Frequency
The maximum allowable operating frequency of the HEY1011 is dependent on the operating ambient air temperature, VDRV voltage level, and the gate charge of the external GaN FET being driven at the OUTPU/OUTPD pins. The total power transferred from VDRV voltage on the primary to the external GaN FET on the secondary increases with gate drive switching frequency and VDRV voltage, hence the IC package must dissipate more heat. The safe operating frequency range is shown in Figure 11, along with the stated values for CLOAD (effective capacitive loading due to the external GaN FET gate), CSEC and VDRV voltage.
Figure 11:HEY1011 Safe operating PWM frequency versus ambient air temperature
VDRV and CSEC Design Guidelines
The output gate drive amplitude is always less than the VDRV voltage.
The OUTPU gate voltage level depends on factors such as VDRV level, CLOAD and CSEC. Figure 12 shows the typical output gate drive amplitude as a function of VDRV and CLOAD, for an assumed value of CSEC as a multiple of CLOAD, for a 50% duty cycle PWM at the IN pin.
Figure 12: Typical Vgate voltage versus VDRV voltage for 4 CLOAD capacitors
Conditions for Figure 12: FIN =100kHz, D = 50%, CSEC = 20*CLOAD
The recommended value for CSEC is approximately 10-20 times CLOAD (the equivalent gate capacitance), to give approximately 5-10% switching ripple on the VSEC rail. Other values can be used, however lower values will result is higher ripple on VSEC. Larger CSEC will require a longer startup time. The maximum recommended value of CSEC = 100 nF should not be exceeded
Bipolar Output Drive
Bipolar output drive is used to provide a negative gate voltage which can be beneficial in protecting against false turn on due to parasitic circuits components. It can be added simply to the HEY1011 by including three extra small external components. For full details see the Heyday application note HD-000222-AN.
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Figure 13: HEY1011 Bipolar drive and recommended PCB layout
RECOMMENDED PCB FOOTPRINT
Figure 15: Recommended PCB footprint