Review of FET Gate drive
There are many good whites papers and application notes published which explain the details of the gate drive voltage and currents for FETs but a brief review is warranted here.
A point worth emphasising here is that it is more important to think in terms of charge transfer rather than simply charging the input capacitance, CISS, of the FET to turn it on. Furthermore, it can be seen in Figure 1 below, FET capacitances are highly non-linear. Capacitance depends largely on the FET VDS.
Figure 1 below shows an overview of the voltages and currents in a half bridge circuit. The zoom in detail shows the turn on of the high side FET. The turn off procedure is the reverse of the turn on procedure where charges must be removed from the circuit.
Before time t0, the circuit conditions are:
- The high side FET is completed off
- The low side FET is off and the inductor current is circulating in the low side FET body diode.
- For the time scale of the switching transition, the inductor current is considered to be DC.
t0 – t¬1¬
VGS_H begins to rise towards the threshold voltage, VTH, of the FET. The FET remains off and no drain current, IDS, flows.
The high side FET VDS will be clamped to the supply voltage plus the body diode voltage drop and will remain so until all the inductor current flows in the FET, that is until the body diode is cut off.
During this period, most of the gate drive current is used to charge the gate-source capacitor, CGS. There is negligible change in the gate-drain capacitor, CGD.
t1 – t¬2
At time t1 VGS_H = VTH and the FET begins to conduct. IDS will begin to rise but VDS remains clamped by the body diode.
The gate current continues to flow into the CGS and CGD capacitors.
Since VDS is clamped by the body diode to VDD + VBD and VGS¬ is rising towards the plateau level, VGP, the charge during this interval can be estimated as:
t2 – t¬3
At time t2 the FET current, IDS, has reached the inductor current level. No current flows in the body diode so the drain-source voltage, VDS, will begin to fall.
Furthermore, since we are operating in the saturation region of the FET output characteristic, it can be seen in Figure 1 below that the gate-source voltage, VGS, remains constant for a fixed value of IDS for varying VDS. Hence, VGS, is fixed at a plateau level, VGP. This region is the well documented Miller plateau.
During this period the gate current is used to charge the gate-drain capacitor, CGD and the charge required can be estimated as: 
t3 – t¬4
At time t3, the FET is fully on and enters the Ohmic region of the output characteristic where the voltage across the FET is determined by the current, IDS and the on-resistance, RDS_ON.
VGS continues to increase to further enhance the channel until it reaches the supply voltage of the driver, VG¬_DRV.
Effect of circuit parasitics on gate drive
In any electronic circuit there are many parasitic components which do not appear on the schematic. FET and IC bond wires and packaging along with PCB traces result in unwanted parasitic inductances. FET internal structures and overlapping PCB traces and power planes add circuit node capacitances.
In most cases these parasitic components have little or no impact on a circuits performance. However, in power switching circuits they can have a severe effect and should be carefully considered.
The internal structure, packaging and pinout of the Heyday HEY1011-AL12 FET driver have been optimised to minimise such parasitics.
The best and most effective way to reduce the external circuit parasitics is through good PCB layout. For further details see the Heyday application note Minimising-pcb-parasitic-effects-with-optimum-layout-of-the-gate-driver-loop.
Figure 2 below shows a simple half bridge power section. This circuits shows the main parasitic components:
- CGS, CGD and COSS are the well documented FET internal capacitances.
- LG represents the gate driver output including the driver IC package and PCB traces.
- LCS represents the common source inductance; that is, inductance that is shared by the gate drive loop and the power commutation loop. It is made up of FET package inductance and PCB traces. This is the most critical parasitic component and should be minimised through good design and FET choice.
- Ls represents the inductance in the source power loop.
- LD represents the drain inductance, both FET package and PCB.
Figure 2: Effects of circuit parasitics
False FET turn on
Due to the high rate of change of voltages and currents in power switching circuits, inductor currents and capacitor voltage drops can be created.
One such example is the false turn on of a FET due to a dv/dt event. Figure 2 above shows the case of the false turn on of the low side FET. After the low side FET has been turned off and a suitable dead-time elapsed, the high side FET is turned on. This produces a rapidly changing switch node voltage at the drain of the low side FET. The resulting capacitor current: 
flowing in the gate-drain capacitance, CGD and driver output will cause the voltage on the gate of the low side FET to rise. If this voltage spike peaks beyond the threshold voltage VTH, the FET will conduct. Considering that the high side FET is also conducting, this can result in a potentially destructive shoot-through event.
Furthermore, it should be remembered as shown in the typical FET capacitor characteristics of Figure 1 above, the capacitors are highly non linear and a function of VDS. Therefore, the effect of iCGD can be more pronounced at lower values of VDS.
This inevitable iCGD current must be managed correctly and also emphasises the importance of a strong driver pull down and correct choice of gate resistor. The HEY1011 driver has independent pull-up and pull down outputs allowing independent choice of both resistors.
Bipolar output drive
A popular method to further mitigate the effects of false turn on is through the use of a bipolar output drive as shown in Figure 3 below.
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Figure 3: Bipolar Output Drive
Here, a suitable choice of driver supply voltage, CSEC, and zener diode generates the VG+ = VZ and VG- = CSEC – VZ voltages.
As emphasised above, PCB layout is critical for the correct performance of power switching circuits. The Heyday HEY1011 driver pinout easily facilitates this bipolar drive circuit without compromising on the key PCB layout guidelines.